Computer chips of the future may have an entirely new shape thanks to collaboration between UCSB and Boeing.

The Boeing Company gave four patents to UCSB that describe technology used in making multi-layered, three-dimensional microchips. Kaustav Banerjee, an assistant professor of electrical and computer engineering, is leading the project and said he hopes to use the patents to build prototypes of the new chips.

A chemical etching process performed on a flat silicon wafer makes traditional integrated circuits, such as the Intel Pentium line. The new multi-layering techniques outlined in the patents describe how to build an integrated circuit in layers stacked to produce a three-dimensional shape, Banerjee said.

The new method saves space, by giving the integrated circuit a smaller footprint, but the real benefits include huge speed increases, versatility and lower heat production. Also, the prestige of having the patents may entice organizations to grant UCSB money for further research, Banerjee said.

“The patents are useful in multiple ways,” Banerjee said. “If we show that we have these patents in our portfolio, it strengthens the proposal.”

Boeing decided to donate the patents to UCSB because they are not ready to fully develop the idea yet, Banerjee said.

“UC Santa Barbara has some of the leading experts in the world in advanced 3-D packaging for integrated circuits,” said Gene Partlow, vice president for the Boeing Intellectual Property Business.

UCSB will be able to refine the technique and continue research into the new design. The industry has known about multi-layered integrated circuits for a while, but was unable to develop them due to manufacturing limitations.

“People have tried it in the past. The technology came out first in the early ’80s,” Banerjee said. “It’s only because of advancements in the process technology and the packaging, a lot of companies in Japan are starting to look at it again.”

One of the major benefits of the stacked design is that the wiring from one part of the chip to another can be shorter, Banerjee said. In a conventional flat chip design, a wire must run from one edge clear across the surface to send a signal.

In a stacked design, the wire may be able to connect two layers vertically, which can be a much shorter distance. This design allows for much improved performance and lower heat production.

Another benefit of building a chip in layers is that all of the layers need not be built from the same material, classically silicon.

“UCSB has been traditionally strong in non-silicon semiconductors. This 3-D idea opens up this new door for multi-faculty collaboration,” Banerjee said.

In a chip built from different materials, engineers would be able to choose layers that are specific to their best function. Such a motley chip is a new idea.

“I am going to use silicon for that part of the chip for what it does the best, which is computation,” Banerjee said. “Maybe I would use indium phosphate for some other application, like photonics, then integrate them together.”

Combining the silicon and non-silicon semiconductors allows chip designers to send information via light. This study of this process is known as photonics. Non-silicon semiconductors are used in photonics for devices such as LEDs. With the advent of the multi-layering technique, a silicon layer can electrically send information to a non-silicon layer, where it is converted to light and sent outside the chip, Banerjee said.

This is accomplished by using information contained in one of the patents, which pertains specifically to optical light guides, Banerjee said. The light guides may be a useful as an internal or external part of the 3-D integrated circuits.

Sending information via light could be beneficial because it does not have the electrical problems that copper wires do.

Additionally, heat management is more of a problem in the three-dimensional integrated circuits than it is in conventional circuits because there is less surface area to dissipate the heat, Banerjee said.

“The fourth patent, which is also very important, relates to heat removal,” said Banerjee. “When you make this 3-D package, the upper layers are going to generate heat, and typically the heatsink is attached to only one side of the chip.”

One of the patents describes a particular way to use tiny heat-moving devices called Peltier junctions to control the heat distribution within the layered integrated circuit.

“There are some areas that are very hot, so maybe we can use these devices in a clever way to remove the heat,” Banerjee said.

“The entire school is going to benefit,” Banerjee said. “It also helps establish a relationship between this big company and our campus.”